Instruction Scheduling Using Simulated Annealing

Most nodes of modern massively-parallel computing systems contain processors that use instruction-level parallelism to increase the speed of the individual processor. In order to achieve the greatest speedup possible, the compiler must perform instruction scheduling so that instructions are presented to the processor in the order that is most efficient. Instruction scheduling is a compiler problem that, due to its NP-complete nature, requires heuristic solutions for any significant programs. One promising stochastic search technique that shows promise in the realm of instruction scheduling is the use of simulated annealing (SA.) Simulated annealing can be thought of as modified hill-climbing that includes “occasional perturbations” in the search space under investigation to avoid the problem of getting stuck in a local minimum or maximum. The process gets its name from the fact that it closely follows the physical process of annealing which is gradual cooling of a liquid until it solidifies. We implemented an SA-driven instruction scheduler in our compiler for instruction-level parallel (ILP) architectures. This allows us to compare our SA instruction scheduler with a more traditional list scheduling approach. Experimental comparison of 114 data dependence graphs efficiency improvement of more than 6% when using an SAdriven scheduler over results obtainable with the standard list scheduling technique.